SystemVerilog and UVM verification work awaits at Synopsys in Markham or Mississauga, validating high-speed mixed-signal products. This senior engineering position supports verification for Backplane Ethernet, PCIe, SATA, and USB SERDES products. You will work with digital and mixed-signal engineers across test planning, simulation, and product validation. The work includes constrained-random verification, coverage analysis, assertions, and debugging. Key Responsibilities:
Create and update test plans and test cases Write modular Verilog, SystemVerilog, UVM, and VMM testbenches Develop SystemVerilog assertions and functional coverage Monitor regressions and debug RTL and gate-level failures Track issues in Jira and document findings in Confluence Requirements:
BS or MS in Electronics, Electrical Engineering, or related fields 8+ years using digital verification methodologies such as VMM or UVM Experience writing Verilog and SystemVerilog test cases Knowledge of high-speed digital and mixed-signal design Familiarity with C/C++, RISC processors, Python, or Perl Apply digital verification expertise, coverage analysis, and debugging skills to Synopsys SERDES development in Markham or Mississauga.
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Senior ASIC Digital Verification Engineer in Markham employer: Synopsys
At Synopsys, we pride ourselves on being an exceptional employer that fosters a culture of innovation and collaboration in Nepean, Ontario. Our commitment to employee growth is evident through comprehensive health and wellness benefits, mentorship opportunities, and a supportive environment that encourages professional development. Join us to lead a talented team in delivering cutting-edge engineering solutions while enjoying a workplace that values diversity and empowers you to make a meaningful impact.
