Senior Lead, High-Performance Package Design

Senior Lead, High-Performance Package Design

Full-Time 109440 - 133760 $ / year (est.) On-site
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At a Glance

  • Tasks: Lead innovative test-chip packaging projects and collaborate with teams to optimize performance.
  • Company: Synopsys Inc, a leader in high-performance design technology.
  • Benefits: Competitive salary, health benefits, and opportunities for professional growth.
  • Other info: Join a dynamic team in Ottawa with excellent career advancement opportunities.
  • Why this job: Make an impact in cutting-edge technology while leading exciting packaging initiatives.
  • Qualifications: Experience in package design and strong communication skills required.

The predicted salary is between 109440 - 133760 $ per year.

Synopsys Inc in Ottawa is seeking a senior package design engineer to lead IP test-chip packaging initiatives.

You’ll drive 4–6 test-chip package designs annually from requirements through delivery, collaborating with internal teams, customers, and partners to optimize SI/PI performance.

You’ll apply 3D EM modeling with HFSS, define layer stacks, and guide customers through architecture evaluations, balancing electrical performance with manufacturability and cost.

English communication required.

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Senior Lead, High-Performance Package Design employer: Synopsys Inc

Join a forward-thinking company that values innovation and collaboration in the semiconductor industry. As an Innovative Project Engineering Manager, you'll thrive in a dynamic work culture that encourages professional growth and offers opportunities to lead groundbreaking Silicon IP projects. Located in a tech hub, our company provides competitive benefits and a supportive environment where your expertise will drive meaningful advancements in technology.

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Contact Details:

Synopsys Inc Recruitment Team

We think you need these skills to ace Senior Lead, High-Performance Package Design

Package Design Engineering
IP Test-Chip Packaging
3D EM Modeling
HFSS
SI/PI Performance Optimization
Layer Stack Definition
Architecture Evaluations