Senior Analog Architect, SerDes & High-Speed IP Lead in Mississauga

Senior Analog Architect, SerDes & High-Speed IP Lead in Mississauga

Mississauga Full-Time 108000 - 132000 $ / year (est.) On-site
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At a Glance

  • Tasks: Lead the design of SerDes circuits and collaborate with digital teams for optimal performance.
  • Company: Join Synopsys Inc., a leader in innovative semiconductor solutions.
  • Benefits: Enjoy competitive salary, health benefits, and opportunities for mentorship.
  • Other info: Be part of a dynamic team focused on advanced technology and career growth.
  • Why this job: Shape the future of connectivity with cutting-edge analog design and impactful projects.
  • Qualifications: Proven experience in analog design and strong leadership skills.

The predicted salary is between 108000 - 132000 $ per year.

Synopsys Inc. seeks a visionary analog designer to own Ser Des macro circuits, driving architecture, verification, and layout excellence.

You will lead sub-block progress, refine analog specifications, and optimize for power, area, and performance while collaborating with digital RTL teams.

The role emphasizes mentorship, rigorous verification, and documentation of design features and test plans, enabling silicon-proven IP products for advanced connectivity.

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Senior Analog Architect, SerDes & High-Speed IP Lead in Mississauga employer: Synopsys Inc

Join a forward-thinking company that values innovation and collaboration in the semiconductor industry. As an Innovative Project Engineering Manager, you'll thrive in a dynamic work culture that encourages professional growth and offers opportunities to lead groundbreaking Silicon IP projects. Located in a tech hub, our company provides competitive benefits and a supportive environment where your expertise will drive meaningful advancements in technology.

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Contact Details:

Synopsys Inc Recruitment Team

We think you need these skills to ace Senior Analog Architect, SerDes & High-Speed IP Lead in Mississauga

Analog Design
SerDes Macro Circuits
Architecture Development
Verification Techniques
Layout Excellence
Power Optimization
Area Optimization