Senior ASIC Design Verification Engineer in Vancouver

Senior ASIC Design Verification Engineer in Vancouver

Vancouver Full-Time 135000 - 165000 $ / year (est.) On-site
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At a Glance

  • Tasks: Lead ASIC verification for innovative AR display technology using UVM and SystemVerilog.
  • Company: Join Snap Inc., a leader in augmented reality innovation.
  • Benefits: Competitive salary, health benefits, and opportunities for professional growth.
  • Other info: Dynamic office environment with a focus on collaboration and innovation.
  • Why this job: Be at the forefront of AR technology and make a real impact on future designs.
  • Qualifications: 10+ years in ASIC Design Verification with strong UVM and SystemVerilog skills.

The predicted salary is between 135000 - 165000 $ per year.

Lead ASIC verification for Snap Inc.’s Spectacles Team, using UVM, SystemVerilog, and Siemens Questa in an office-based model. This engineer designs verification for display Integrated Circuits supporting augmented reality. The work spans digital design, analog logic, software, and verification collaboration. You will build testbenches, execute coverage-driven plans, automate tools, and debug simulations.

Key Responsibilities:

  • Design display Integrated Circuits for augmented reality
  • Develop UVM-based and assertion-based testbenches
  • Create functional and code coverage verification test plans
  • Use Siemens Questa for verification and debugging
  • Specify tools and create automation

Requirements:

  • BSEE, MSEE, or relevant years of experience
  • 10+ years of ASIC Design Verification experience
  • Strong UVM and SystemVerilog knowledge
  • Digital simulation and Verilog RTL practices
  • Linux scripting with TCL, Make, Perl, Python, or Shell
  • Apply ASIC verification expertise, coverage planning, SystemVerilog, and automation to Snap’s AR display circuit development.

Senior ASIC Design Verification Engineer in Vancouver employer: Snap Inc.

At Bitmoji, we foster a vibrant and inclusive work culture that encourages creativity and innovation, making it an exceptional place for Software Engineers to thrive. Located in a dynamic environment, our employees enjoy comprehensive benefits, including generous parental leave, wellness programs, and opportunities for professional growth through educational workshops and team outings. Join us to be part of a team that values your contributions and empowers you to make a meaningful impact on how people express themselves online.

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Contact Details:

Snap Inc. Recruitment Team

We think you need these skills to ace Senior ASIC Design Verification Engineer in Vancouver

UVM
SystemVerilog
Siemens Questa
ASIC Design Verification
Testbench Development
Functional Coverage
Code Coverage Verification