At a Glance
- Tasks: Lead and execute innovative Physical Design for cutting-edge SoC and retimer ASICs.
- Company: Join Qualcomm, a leader in technology innovation and smart connectivity.
- Benefits: Competitive salary, bonuses, RSU grants, and a comprehensive benefits package.
- Other info: Dynamic work environment with opportunities for growth and development.
- Why this job: Make an impact on next-gen tech while collaborating with top engineering talent.
- Qualifications: Master's or Bachelor's degree in Engineering with relevant experience in ASIC design.
The predicted salary is between 20000 - 174200 $ per year.
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next‑generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.
What You'll Do
- Lead and execute end‑to‑end Physical Design flow for SoC and retimer ASICs, including:
- Floorplanning
- Clock Tree Synthesis (CTS)
- Placement & Routing
- Power Delivery Network (PDN)
- Timing analysis and closure
- Plan and implement full‑chip or hierarchical designs, including full‑reticle‑scale integration
- Drive timing closure across all corners and modes (MMMC), including SI‑aware optimization
- Perform and review physical verification checks: DRC, LVS, Design‑for‑manufacturability (DFM), Design‑for‑yield (DFY)
- Collaborate with cross‑functional engineering teams (front‑end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness
- Lead integration of high‑speed SerDes macros and mixed‑signal IP, ensuring robust floorplan and signal integrity alignment
- Drive IR/EM closure, power optimization, and congestion mitigation for large die designs
- Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts
- Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions
- Develop and improve physical design methodologies and flows to enhance efficiency and scalability
What You'll Need
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR Bachelor's degree and 4+ years of progressive experience in ASIC Physical Design or related domain
- Strong experience with:
- End‑to‑end ASIC Physical Design flow
- Timing closure and signoff methodologies
- Physical verification flows
- Hands‑on expertise in industry‑standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2)
- Solid understanding of:
- Power delivery and reliability (IR/EM)
- Clocking architectures and CTS
- Large‑scale SoC integration challenges
- Preferred Qualifications
- Experience with high‑speed SerDes / retimer designs (PAM4‑class signaling)
- Experience with full‑reticle or near‑reticle SoC implementation
- Familiarity with multi‑die / chiplet / advanced packaging architectures
- Exposure to data center, networking, or optical connectivity ASICs
- Strong scripting and automation skills (Python, Tcl)
- Proven ability to lead complex PD execution in high‑pressure tapeout environments
- Strong analytical and problem‑solving skills with attention to detail
- Ability to synthesize ambiguous or conflicting requirements into execution plans
- Effective collaboration across global, cross‑functional engineering teams
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Key Competencies
Minimum Qualifications
Staff Engineer, Physical Design/Implementation in Toronto employer: Qualcomm
Qualcomm Canada ULC is an exceptional employer that fosters a collaborative and innovative work culture, making it an ideal place for Display Silicon System Debug Engineers to thrive. With a strong emphasis on employee growth, you will have access to mentorship opportunities and the chance to work alongside industry leaders in a cutting-edge environment. Located in Canada, the company offers competitive benefits and a commitment to work-life balance, ensuring that you can pursue meaningful and rewarding employment while contributing to groundbreaking technology.
We think you need these skills to ace Staff Engineer, Physical Design/Implementation in Toronto
End-to-end ASIC Physical Design flow
Timing closure and signoff methodologies
Physical verification flows
Industry-standard EDA tools (e.g., Cadence Innovus, Synopsys ICC2)
Power delivery and reliability (IR/EM)
Clocking architectures and CTS
Large-scale SoC integration challenges
