Staff Digital Design Verification Engineer in Toronto

Staff Digital Design Verification Engineer in Toronto

Toronto Full-Time 67500 - 82500 $ / year (est.) On-site
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At a Glance

  • Tasks: Design and verify high-performance, low-power products using cutting-edge technology.
  • Company: Join Qualcomm Canada, a leader in tech innovation based in Toronto.
  • Benefits: Enjoy competitive pay, health benefits, and opportunities for remote work.
  • Other info: Collaborative environment with great potential for career advancement.
  • Why this job: Make an impact in the tech world while working on exciting projects.
  • Qualifications: Expertise in Verilog/SystemVerilog, UVM, and verification processes required.

The predicted salary is between 67500 - 82500 $ per year.

Qualcomm Canada ULC in Toronto is seeking an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP development for high performance, low power products. You will collaborate across cross-functional groups to determine product execution path, with a focus on end-to-end verification and IP delivery.

The role requires strong expertise in Verilog/SystemVerilog, UVM, and constrained-random verification.

Staff Digital Design Verification Engineer in Toronto employer: Qualcomm

Qualcomm Canada ULC is an exceptional employer that fosters a collaborative and innovative work culture, making it an ideal place for Display Silicon System Debug Engineers to thrive. With a strong emphasis on employee growth, you will have access to mentorship opportunities and the chance to work alongside industry leaders in a cutting-edge environment. Located in Canada, the company offers competitive benefits and a commitment to work-life balance, ensuring that you can pursue meaningful and rewarding employment while contributing to groundbreaking technology.

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Contact Details:

Qualcomm Recruitment Team

We think you need these skills to ace Staff Digital Design Verification Engineer in Toronto

ASIC Design
Verilog
SystemVerilog
UVM
Constrained-Random Verification
IP Development
End-to-End Verification