Memory Subsystem Verification Engineer in Vancouver

Memory Subsystem Verification Engineer in Vancouver

Vancouver Full-Time 96750 - 118250 $ / year (est.) On-site
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At a Glance

  • Tasks: Develop and implement verification strategies for cutting-edge memory subsystems.
  • Company: Join Qualcomm Canada, a leader in tech innovation and design.
  • Benefits: Competitive salary, health benefits, and opportunities for remote work.
  • Other info: Dynamic work environment with great potential for career advancement.
  • Why this job: Be part of a team that shapes the future of high-performance memory technology.
  • Qualifications: Experience in digital design verification and strong problem-solving skills.

The predicted salary is between 96750 - 118250 $ per year.

Qualcomm Canada ULC is seeking a motivated and experienced Design Verification Engineer to join its memory subsystem verification team.

The role focuses on developing verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM interfaces, PHY‑related logic, and high‑performance memory subsystems.

Replacement Position.

This role involves full verification lifecycle: plan development, UVM‑based testbenches, assertions, simulations, debugging failures, and

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Memory Subsystem Verification Engineer in Vancouver employer: QUALCOMM, Inc.

Qualcomm Canada ULC is an exceptional employer that fosters a dynamic work culture focused on innovation and collaboration in the field of AI and machine learning. Located in a vibrant tech hub, employees benefit from competitive compensation, a comprehensive benefits package, and ample opportunities for professional growth and development. Join a team that not only values your contributions but also supports your journey in shaping the future of connected devices.

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Contact Details:

QUALCOMM, Inc. Recruitment Team

We think you need these skills to ace Memory Subsystem Verification Engineer in Vancouver

Verification Strategies
Digital Design Verification
Memory Controllers
DDR/LPDDR/HBM Interfaces
PHY-related Logic
High-performance Memory Subsystems
UVM-based Testbenches