A leading semiconductor company is seeking an RTL/FPGA Design Engineer with over 15 years of experience. The ideal candidate should have a bachelor's degree in engineering or computer science and possess excellent skills in RTL design using Verilog and System Verilog. Key responsibilities include working with EDA tools and knowledge of networking standards. This contract position offers a pay range of CA$110.00/hr to CA$135.00/hr.
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Senior RTL/FPGA Design Eng - Verilog, Vivado, CDC (Contract) in Ottawa employer: LanceSoft, Inc.
As an Enterprise Digital Transformation Specialist, you will thrive in a dynamic work environment that champions innovation and collaboration. Our company prioritizes employee growth through continuous learning opportunities and a supportive culture that values diverse perspectives. Located in a vibrant city, we offer unique advantages such as access to cutting-edge technology and a network of industry leaders, making it an excellent place for professionals seeking meaningful and rewarding careers.
