At a Glance
- Tasks: Design and implement FPGA logic, collaborating with teams to deliver top-notch solutions.
- Company: Join a growing engineering team in Ottawa focused on innovation.
- Benefits: Stable, long-term opportunity with potential for career growth.
- Other info: On-site position in Ottawa with a dynamic work environment.
- Why this job: Take ownership of complex designs and make a real impact in tech.
- Qualifications: 10-15 years of FPGA design experience and strong SystemVerilog skills.
The predicted salary is between 134190 - 164010 $ per year.
We’re looking for an experienced FPGA Design Engineer to join a growing engineering team in Ottawa.
You’ll take ownership of FPGA designs from specification through implementation, working closely with hardware, verification, and systems teams to deliver robust, production-quality solutions.
This is a full-time, on-site position in Ottawa, ideal for someone looking for a stable, long-term opportunity with the potential to grow into a Design Prime role within the first few years.
Key Responsibilities
Design and implement FPGA logic using System Verilog, from micro-architecture through to timing-clean implementation.
Analyse and manage Clock Domain Crossings (CDC), including synchronization strategies and CDC verification.
Own the FPGA synthesis flow, including tool configuration, timing constraints, and timing closure.
Analyse synthesis and timing reports to identify and resolve timing, congestion, and resource utilisation issues.
Collaborate with hardware, verification, and systems teams to ensure designs are robust, testable, and implementation-ready.
Contribute to design reviews, technical documentation, and improvements to FPGA design processes.
Must-Have Experience
10-15 years of hands-on FPGA design experience, with the ability to quickly take ownership of complex designs.
Strong, current experience with System Verilog.
Practical experience with CDC analysis and implementation.
Hands-on experience configuring FPGA synthesis tools.
Strong understanding of SDC timing constraints and constraint development.
Proven ability to analyse synthesis/timing reports and drive designs through timing closure.
Ability to work full-time, on-site in Ottawa.
Nice to Have
Experience with UVM-based verification.
Scripting experience with Tcl, Python, or similar.
Familiarity with high-speed interfaces used in optical, networking, or communications products.
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