Senior ASIC RTL Architect for High-Performance IP

Senior ASIC RTL Architect for High-Performance IP

Full-Time On-site
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At a Glance

  • Tasks: Translate architectural requirements into synthesizable SystemVerilog/Verilog for high-performance ASIC projects.
  • Company: Join a leading European recruitment firm working with top North American clients.
  • Benefits: Competitive salary, flexible work options, and opportunities for professional growth.
  • Other info: Collaborative environment with a focus on innovation and career advancement.
  • Why this job: Be at the forefront of cutting-edge technology and make a significant impact in the industry.
  • Qualifications: Experience in ASIC design and strong skills in SystemVerilog/Verilog.

European Recruitment BV is seeking experienced Verification engineers in Ottawa to work on leading-edge ASIC projects for North American clients. You will translate architectural requirements into synthesizable SystemVerilog/Verilog, owning blocks from spec through front-end sign-off, with a focus on power, performance and physical implementation.

You will collaborate with architecture, RTL, firmware, DV, and PD teams to deliver complex, high-performance silicon and meet project milestones.

Senior ASIC RTL Architect for High-Performance IP employer: European Recruitment BV

European Recruitment BV is an exceptional employer, offering a dynamic work environment in Ottawa where innovation thrives. With a strong focus on employee growth and collaboration, you will have the opportunity to work on cutting-edge ASIC projects while enjoying a supportive culture that values your contributions. The company provides competitive benefits and fosters a community of professionals dedicated to excellence in high-performance silicon design.

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Contact Details:

European Recruitment BV Recruitment Team

We think you need these skills to ace Senior ASIC RTL Architect for High-Performance IP

SystemVerilog
Verilog
ASIC Design
Architectural Requirements Translation
Power Optimization
Performance Optimization
Physical Implementation