Principal Digital Verification Lead in Ottawa

Principal Digital Verification Lead in Ottawa

Ottawa Full-Time 120690 - 147510 $ / year (est.) On-site
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At a Glance

  • Tasks: Lead verification of Forward Error Correction IP and develop innovative verification plans.
  • Company: Ciena, a leader in digital networking solutions with a focus on collaboration.
  • Benefits: Attractive salary, health benefits, and opportunities for professional growth.
  • Other info: Dynamic work environment in Ottawa with excellent career advancement potential.
  • Why this job: Join a cutting-edge team and make a significant impact in digital verification.
  • Qualifications: 10+ years in verification with expertise in C/C++, SystemVerilog, and UVM.

The predicted salary is between 120690 - 147510 $ per year.

Ciena is seeking a Digital Verification Engineer (FEC) in Ottawa to lead verification of Forward Error Correction IP.

You will develop verification plans, validate architectural blocks, and collaborate with ASIC teams to ensure robust design verification through simulation, formal methods, and coverage-driven approaches.

The role requires 10+ years in verification, a BS in Electrical/CS/Software, and strong skills in C/C++, System Verilog, UVM, SVA, and simulators.

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Principal Digital Verification Lead in Ottawa employer: ciena

Ciena is an exceptional employer that prioritizes innovation, collaboration, and employee well-being in the heart of Ottawa. With a strong commitment to professional growth, Ciena offers extensive development opportunities, a comprehensive benefits package, and a flexible work culture that empowers employees to thrive both personally and professionally. Join us to be part of a team that shapes the future of networking while enjoying a supportive environment that values diversity and inclusion.

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Contact Details:

ciena Recruitment Team

We think you need these skills to ace Principal Digital Verification Lead in Ottawa

Digital Verification
Forward Error Correction (FEC)
Verification Plans Development
Architectural Block Validation
Collaboration with ASIC Teams
Simulation Techniques
Formal Methods