Ciena Corporation in Ottawa is seeking a senior ASIC backend designer to drive physical design, floorplanning, and timing closure for high-performance networks. You will work with RTL teams to integrate analog blocks and optimize PPA while leveraging advanced EDA flows.
The role emphasizes scripting, formal verification, and STA analysis to ensure signoff-quality results on tight submicron nodes. A strong collaboration with tool vendors and cross-functional teams is essential.
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Senior ASIC Physical Design Engineer – PPA & Timing Leader in Ottawa employer: Ciena Corporation
Ciena is an exceptional employer that prioritizes a people-first approach, fostering a flexible work environment that encourages individual growth and well-being. Located in Ottawa, our culture emphasizes innovation and collaboration, providing employees with opportunities to contribute to cutting-edge technology while making a meaningful impact on society. With a comprehensive benefits package and a commitment to diversity and inclusion, Ciena is dedicated to creating a workplace where every employee feels valued and empowered.
