Ciena Corporation in Ottawa is seeking a hardware-focused ASIC design engineer to design mixed-signal macros within an ASIC flow for high-baud-rate optical modems.
You will generate Verilog, SPICE netlists, and provide IP integration support, using Cadence and Synopsys tools. This role emphasizes analog/digital timing handoff and test methodologies.
The team collaborates across analog and digital disciplines, applying rigorous design and verification practices.
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Mixed-Signal IP Integration Engineer: High-Speed ASICs in Ottawa employer: Ciena Corporation
Ciena is an exceptional employer that prioritizes a people-first approach, fostering a flexible work environment that encourages individual growth and well-being. Located in Ottawa, our culture emphasizes innovation and collaboration, providing employees with opportunities to contribute to cutting-edge technology while making a meaningful impact on society. With a comprehensive benefits package and a commitment to diversity and inclusion, Ciena is dedicated to creating a workplace where every employee feels valued and empowered.
