At a Glance
- Tasks: Design and validate high-speed clocking for next-gen optical transceivers.
- Company: Celero Communications, a leader in innovative tech solutions.
- Benefits: Competitive salary, health benefits, and opportunities for professional growth.
- Other info: Hands-on lab work and system-level validation in a dynamic environment.
- Why this job: Join a cutting-edge team and shape the future of high-speed technology.
- Qualifications: Master’s or PhD in EE with 5+ years in PLL design.
The predicted salary is between 108000 - 132000 $ per year.
Celero Communications, Inc. is seeking a Principal PLL Design Engineer in Ottawa to drive high-speed clocking design for next‑gen optical transceivers and SerDes. The role focuses on designing and validating PLLs, VCOs and related analog blocks in advanced CMOS nodes, with hands-on lab bring-up and system-level validation.
The ideal candidate has:
- A Master’s or PhD in EE
- 5+ years in PLL design
- Proficiency in Cadence Virtuoso and MATLAB
- Strong documentation and cross‑functional skills
Senior PLL Design Architect for High-Speed Transceivers employer: Celero Communications, Inc.
At Celero Communications, Inc., we pride ourselves on fostering a collaborative and innovative work environment in Ottawa, where our employees are empowered to push the boundaries of technology in high-speed clocking design. We offer competitive benefits, continuous professional development opportunities, and a culture that values creativity and teamwork, making it an ideal place for talented engineers to thrive and contribute to cutting-edge projects in optical transceivers and SerDes.
Contact Details:
Celero Communications, Inc. Recruitment Team
