Senior High-Speed Analog Layout Lead

Senior High-Speed Analog Layout Lead

Full-Time 121455 - 148445 $ / year (est.) On-site
C

At a Glance

  • Tasks: Lead the layout of high-performance analog/mixed-signal IP blocks for optical communication.
  • Company: Celero Communication Inc., a leader in innovative optical technology.
  • Benefits: Competitive salary, mentorship opportunities, and a collaborative work environment.
  • Other info: Join a dynamic team with global reach and exciting career growth potential.
  • Why this job: Make an impact in cutting-edge optical communication systems while mentoring future engineers.
  • Qualifications: Experience in analog layout design and strong collaboration skills.

The predicted salary is between 121455 - 148445 $ per year.

Celero Communication Inc. is seeking a Principal/Senior Analog Layout Engineer to drive the layout of analog/mixed-signal IP blocks for high‑performance optical communication systems.

You will collaborate with circuit designers, CAD/PDK teams, and other layout engineers to ensure first‑pass silicon success.

You will lead floor planning, layout of ADCs/DACs/PLLs, mentor junior engineers across time zones, and perform LVS, DRC, PERC signoffs.

#J-18808-Ljbffr

Senior High-Speed Analog Layout Lead employer: Celero Communications, Inc.

At Celero Communications, Inc., we pride ourselves on fostering a dynamic and innovative work culture that empowers our employees to excel in their roles. As a Senior High-Speed Analog IC Designer, you will have access to cutting-edge technology and the opportunity for professional growth within a collaborative team environment. Located in a vibrant startup atmosphere, we offer competitive benefits and a chance to make a significant impact in the rapidly evolving field of AI interconnects.

C

Contact Details:

Celero Communications, Inc. Recruitment Team

We think you need these skills to ace Senior High-Speed Analog Layout Lead

Analog Layout Design
Mixed-Signal IP Blocks
High-Performance Optical Communication Systems
Collaboration with Circuit Designers
CAD/PDK Knowledge
Floor Planning
Layout of ADCs