Senior ASIC Design Engineer

Senior ASIC Design Engineer

Full-Time 112815 - 137885 $ / year (est.) On-site
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At a Glance

  • Tasks: Design high-performance digital circuits and collaborate with cross-functional teams.
  • Company: Fast-growing semiconductor startup in Ottawa with a dynamic culture.
  • Benefits: Competitive salary, flexible work environment, and opportunities for skill development.
  • Other info: Exciting projects with potential for career advancement in a thriving tech environment.
  • Why this job: Join a cutting-edge team and make an impact in the semiconductor industry.
  • Qualifications: Experience in ASIC design, Verilog/SystemVerilog, and strong collaboration skills.

The predicted salary is between 112815 - 137885 $ per year.

Celero Communications is seeking an experienced ASIC Design Engineer to join our fast-growing semiconductor startup in Ottawa. You will design and implement high-performance digital circuits and ASIC blocks using Verilog/SystemVerilog, with exposure to DSP, SerDes, and mixed-signal interfaces.

You will collaborate with Analog, Verification, and Physical Design teams, perform synthesis and timing analysis, develop automation scripts in Python or Tcl, and help drive silicon bring-up from RTL.

Senior ASIC Design Engineer employer: Celero Communications, Inc.

At Celero Communications, Inc., we pride ourselves on fostering a dynamic and innovative work culture that empowers our employees to excel in their roles. As a Senior High-Speed Analog IC Designer, you will have access to cutting-edge technology and the opportunity for professional growth within a collaborative team environment. Located in a vibrant startup atmosphere, we offer competitive benefits and a chance to make a significant impact in the rapidly evolving field of AI interconnects.

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Contact Details:

Celero Communications, Inc. Recruitment Team

We think you need these skills to ace Senior ASIC Design Engineer

ASIC Design
Verilog
SystemVerilog
DSP
SerDes
Mixed-Signal Interfaces
Synthesis