At a Glance
- Tasks: Design and simulate cutting-edge PLL circuits for next-gen AI tech.
- Company: Fast-growing start-up focused on high-speed interconnect technology.
- Benefits: Competitive salary, flexible work environment, and opportunities for growth.
- Other info: Dynamic start-up culture with a focus on innovation and collaboration.
- Why this job: Join a team shaping the future of optical transceivers and high-speed systems.
- Qualifications: Master’s or PhD in Electrical Engineering with 5+ years in PLL design.
The predicted salary is between 120780 - 147620 $ per year.
Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.
What You Will Do
- Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range.
- Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre.
- Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization.
- Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies.
- Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment.
- Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies.
What You Will Bring
- Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
- Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes).
- Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs.
- Proficient in Cadence Virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling.
- Strong communication and documentation skills.
Principal PLL Design Engineer employer: Celero Communications, Inc.
Celero Inc. is an exceptional employer for Principal PLL Design Engineers, offering a dynamic work environment that fosters innovation in High-Speed Interconnect Technology. Located in a vibrant tech hub, the company provides competitive benefits, a collaborative culture, and ample opportunities for professional growth, making it an ideal place for engineers eager to contribute to cutting-edge AI advancements.
Contact Details:
Celero Communications, Inc. Recruitment Team
