Celero Communications, Inc. is seeking a Principal PLL Design Engineer in Ottawa to drive high-speed clocking design for next‑gen optical transceivers and SerDes.
The role focuses on designing and validating PLLs, VCOs and related analog blocks in advanced CMOS nodes, with hands-on lab bring-up and system-level validation. The ideal candidate has a Master’s or PhD in EE with 5+ years in PLL design, proficiency in Cadence Virtuoso and MATLAB, and strong documentation and cross‑functional
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Senior PLL Design Architect for High-Speed Transceivers in Ottawa employer: Celero Communications, Inc.
At Celero Communications, Inc., we pride ourselves on fostering a dynamic and innovative work culture that empowers our employees to excel in their roles. As a Senior High-Speed Analog IC Designer, you will have access to cutting-edge technology and the opportunity for professional growth within a collaborative team environment. Located in a vibrant startup atmosphere, we offer competitive benefits and a chance to make a significant impact in the rapidly evolving field of AI interconnects.
Contact Details:
Celero Communications, Inc. Recruitment Team
