At a Glance
- Tasks: Lead the verification of digital RTL and develop reusable verification components.
- Company: Join Cadence, a leader in technology innovation with a dynamic team.
- Benefits: Enjoy competitive salary, health coverage, RRSP, TFSA, and more.
- Other info: Collaborative environment with opportunities for growth and travel.
- Why this job: Make an impact in tech while working on cutting-edge projects.
- Qualifications: Bachelor's in Electrical/Computer Engineering or Computer Science; understanding of verification methodologies.
The predicted salary is between 60000 - 166400 $ per year.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role is for an existing vacancy.
Overview
This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality. The candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments. It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.
The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status. The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills. The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.
The candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).
Minimum Experience:
- Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
- Understanding of verification architecture and methodologies
- Understanding of Metric Driven Verification
- Understanding of Universal Verification Methodologies
- Understanding of the identification, planning and creation of functional coverage and checks
- Understanding of System Verilog Assertions (SVAs)
- Understanding of digital design flow
Preferred Experience:
- Master of Science in EE/CPE/CSC
- Experience with SystemVerilog UVM coding language is desired
- Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred
- Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
- Exposure to Formal Verification Technologies
- Exposure to Mixed Signal Design experience
- Experience with Cadence tools experience
- Exposure to Low Power verification experience using CPF or UPF
Cadence is an equal-opportunity employer committed to hiring a diverse workforce.
Lead Digital Verification Engineer employer: Cadence Design Systems
At Cadence, we foster a dynamic work environment that encourages innovation and collaboration, making it an exceptional place for a Senior Principal Product Engineer. Our commitment to employee growth is evident through mentorship opportunities and the chance to lead cutting-edge projects in semiconductor design, all while being part of a company recognized as one of the 100 Best Companies to Work For by Fortune Magazine. Located in a vibrant tech hub, we offer competitive benefits and a culture that values diversity and inclusion, ensuring that every team member can thrive and make a meaningful impact.
