ASIC Design Engineer, PCIe IP Enablement in Markham

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THE ROLE: We are seeking a highly motivated ASIC Design Engineer, PCIe IP Enablement to join our team. In this role, you will contribute to the design and development of cutting-edge PCIe solutions, focusing on architecture, IP design, RTL implementation, and front-to-back design flows. You will collaborate closely with cross-functional teams to ensure high-quality, power-efficient, and performance-optimized designs.

THE PERSON: A successful candidate will have ASIC hardware design experience with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.

KEY RESPONSIBILITIES:

• Integration and Implementation of AMD's PCI Express (PCIe) subsystem, IP deployment to SoC.
• Synthesis, timing, lint and CDC closure to ensure high quality design.
• Responsible to implement the design related to test, debug, clocks.
• Understanding of low power design techniques and good knowledge of the UPF based power-aware flow.
• Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
• Drive and hands-on flow development, automation, and scripting.
• Work collaboratively across teams of IP designers, Physical Design team and SoC level leads.
• Technical and schedule discussion with multi-site engineers and managers.

PREFERRED EXPERIENCE:

• Strong understanding of Digital Design in RTL, Verilog HDL.
• Experience with synthesis, linting / CDC tools, equivalence checks.
• Knowledge of power saving techniques, including UPF/CPF based power-aware flows and checks.
• Experience with design flows, version control systems, integration and implementation of IPs to SoC.
• Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA.
• Strong AI knowledge and experience in its usage to develop skills and agents.
• Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD).
• Excellent problem-solving and debugging skills.

ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical Engineering / Computer Engineering preferred. This role is not eligible for Visa sponsorship.