Build FPGA RTL and IP design experience with Altera in Toronto while developing high-speed interfaces for DDR, LPDDR, and MIPI devices.
This student intern role supports Altera's IP Solutions Engineering team. You will develop and verify configurable IP cores integrated with Quartus Prime. The work spans advanced FPGA architectures, RTL implementation, simulation models, and technical documentation for external memory and I/O applications.
Key Responsibilities:
- Design architectures for DDR, LPDDR, and MIPI protocols
- Develop RTL for external memory and I/O interfaces
- Integrate device support with CAD tools
- Create verification frameworks, models, and regression tests
- Support hardware power-on, debugging, and product rollout
Requirements:
- Pursuing a bachelor's degree in engineering or computer science
- At least three months of digital logic design experience
- At least three months using scripting or programming languages
- Strong communication, initiative, problem-solving, and teamwork skills
- FPGA, RTL simulation, or timing analysis experience preferred
Develop practical FPGA RTL, verification, and high-speed interface expertise while contributing to Altera IP solutions in Toronto.
FPGA RTL Design Intern Toronto employer: altera
Altera is an exceptional employer located in the vibrant city of Toronto, offering a dynamic work culture that fosters innovation and collaboration. As a HLS Compiler Engineer, you will benefit from mentorship by seasoned professionals while engaging in meaningful projects that push the boundaries of technology. With a strong focus on employee growth and development, Altera provides unique opportunities to enhance your skills in a cutting-edge field, making it an ideal place for those seeking a rewarding career in hardware synthesis and AI acceleration.
