IP Silicon Firmware Engineer

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you are redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward.

The AMD NBIO Team is on the lookout for a dynamic, upbeat Firmware Engineer to join our growing team, focused on High-Speed I/O (HSIO) and Data Transfer IPs. As a key contributor to the success of AMD’s IP, you will design and deliver scalable firmware solutions that speed up debug and execution during bring-up and validation cycles for a given program, across forthcoming AMD APU, CPU, Compute, and Discrete Graphics SOC programs. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

You have a passion for embedded firmware development and the complex processor architecture and hardware it runs on. You are comfortable working at the boundary between firmware and hardware, and you enjoy building tools and solutions that make debug and validation faster and more reliable. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You are a self-starter with strong analytical and problem-solving skills and are ready to independently drive tasks to completion.

KEY RESPONSIBILITIES:

• Own firmware development and debug tooling for AMD’s HSIO and Data Transfer IPs, partnering closely with hardware design, verification, and diagnostics teams across the SOC bring-up and validation lifecycle.
• Design, develop, and maintain embedded firmware for AMD’s HSIO/Data Transfer IPs, including the firmware/hardware interface, register maps, and programming model, in partnership with RTL/hardware design teams as well as SoC/Platform FW teams.
• Debug firmware and IP issues across the firmware/hardware/RTL boundary, driving failures to root cause during pre-silicon simulation, emulation, bring-up, and system validation.
• Define and execute firmware validation strategy, including unit testing, firmware/RTL co-simulation, and regression automation, for HSIO and Data Transfer features.
• Develop and enhance Python-based tools and infrastructure that accelerate data collection, debug turnaround, and execution of validation test plans.
• Engage on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.
• Support post-silicon bring-up, debug, and firmware validation on silicon, including issues on customer platforms as requested by customer support teams.
• Contribute to design and code reviews, author documentation, and mentor engineers on embedded firmware practice.
• Lead collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.

PREFERRED EXPERIENCE:

• Strong C/C++ programming for resource-constrained, bare-metal/embedded firmware targets.
• Experience developing firmware against hardware register interfaces, including bring-up on pre-silicon models (simulation, emulation, FPGA) and on silicon.
• Demonstrated ability to debug across the firmware/hardware/RTL boundary using source-code debuggers and other system debug tools, driving issues to root cause.
• Extensive experience with ASIC/firmware debug techniques and methodologies.
• Strong scripting skills in Python for tooling, data processing, and automation development.
• Experience with source control systems such as git.
• Knowledge of physical and protocol levels of common high-speed interfaces is a strong asset.
• In-depth knowledge of PC architectures/PCIe protocol is an asset.
• Post-silicon bring-up and debug experience including board/platform-level debug, such as clock/power delivery, sequencing, analysis, and optimization.
• Experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc. is an asset.
• Must have excellent written and verbal communication skills.
• Must excel in a dynamic team working environment.
• Leadership and mentoring skills a definite asset.
• Must be a self-starter and be able to independently drive tasks to completion.

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree majoring in EE, CS, Computer Engineering, or related field.

LOCATION:

Markham, Vancouver