Develop FPGA RTL and IP solutions in Toronto with Altera's PACE team, focusing on high-speed interfaces and digital design verification.
This student intern role supports advanced FPGA architecture, implementation, and verification for configurable IP cores integrated with Quartus Prime. You will work with engineers on PHY-lite, MIPI, and LVDS-based solutions for high-speed data transmission. Collaboration spans silicon design, validation, application engineering, and customer experience teams.
Key Responsibilities:
- Design RTL from video and display protocol specifications
- Develop device support and Quartus Prime CAD integration
- Build verification IP, models, frameworks, and regression tests
- Support hardware power-on, debugging, and product rollout
- Develop examples, simulations, and technical documentation
Requirements:
- Pursuing a relevant bachelor's degree
- Three months' digital logic design or verification experience
- Three months' scripting or software programming experience
- Knowledge of SystemVerilog, Verilog, VHDL, Python, TCL, Perl, or C/C++
- Strong communication, problem-solving, initiative, and teamwork skills
Apply FPGA design, RTL verification, and programming skills to high-speed IP development with Altera's Toronto engineering team.
FPGA RTL Design Intern in Toronto employer: 207 Altera Semiconductor Technology Canada ULC
Altera is an exceptional employer located in the vibrant city of Toronto, Ontario, offering a dynamic work culture that fosters innovation and collaboration. As a Senior Compiler Engineer, you'll not only have the opportunity to lead advancements in EDA tools but also play a pivotal role in mentoring the next generation of engineers, ensuring your professional growth alongside the company's success. With a commitment to employee development and a focus on cutting-edge technology, Altera provides a rewarding environment for those looking to make a meaningful impact in the field of FPGA design.
Contact Details:
207 Altera Semiconductor Technology Canada ULC Recruitment Team
